Complementary metal oxide semiconductor (“CMOS”) image sensors are widely used in digital cameras to produce digital images by converting optical signals into electrical signals. In operation, CMOS image sensors convert an optical signal into an electrical signal using a multitude of pixels that each include a photodiode and a read-out circuit. The photodiode generates electric charges using absorbed light, converts the generated electric charges into an analog current, and delivers the analog current to the read-out circuit. The read-out circuit converts the analog signal into a digital signal and outputs the digital signal.
Certain CMOS image sensor pixel circuits are formed using four transistors and are known and referred to as 4T image sensor pixels or “4T pixels.” FIG. 1 illustrates a typical design of a 4T pixel 10 connected to a bitline 20. As shown, the 4T CMOS image sensor pixel 10 includes a photodiode (“PD”) that provides the photon to electron conversion, while a floating diffusion (“FD”) point provides the electron to voltage conversion. The voltage per electron conversion of the FD is known as conversion gain (“CG”) and is an important parameter for CMOS image sensors. Conversion gain boosts the pixel signal relative to the analog noise, thereby reducing the noise floor, and thereby enabling performance at lower light levels.
For such CMOS image sensors, during the analog-to-digital conversion process, a comparator receives an analog voltage and compares the analog voltage with a ramp voltage. In one implementation of a CMOS image sensor, the comparator compares the analog voltage with the ramp voltage, and uses a counter to count until the ramp voltage is greater than an analog voltage. Once the counter stops counting, a count value is digital data corresponding to an analog voltage, that is, the count value is the digital data into which the analog voltage has been converted.
In any event, it is understood to those skilled in the art that an up-down counter is typically used to perform digital double sampling (“DDS”). DDS means obtaining a difference (Dsig−Drst) between digital data Drst obtained by converting a first analog signal output by an initialized pixel into digital data, and digital data Dsig obtained by converting a second analog signal received from the pixel that has received an external image signal into digital data, wherein the second analog signal corresponds to the external image signal. Referring to FIG. 1, the pixel is reset when the reset transistor (“RST”) and transfer gate (“TG”) are turned on simultaneously, setting both the floating diffusion FD and the photodiode PD to the VDD voltage level. Next, the transfer gate TG is turned off (disconnecting the photodiode PD and floating diffusion FD) and the photodiode PD is left to integrate light.
After integration, the signal measurement occurs. First, the reset transistor RST is turned on and off to reset the floating diffusion FD. Immediately after this, the reset level is sampled from the floating diffusion FD and stored on the column circuit, i.e., bitline 20. Next, the transfer gate TG is turned on and off which allows charge on the photodiode PD to transfer to the floating diffusion (FD). Once the charge transfer is complete, this charge (the photodiode signal level plus the floating diffusion reset level) is measured and stored on bitline 20 as well.
These two stored voltages are then differenced (Dsig−Drst) to determine the photodiode signal level. This design allows for correlated double sampling (“CDS”) operation to occur, as the reset level used to determine the absolute pixel level is now measured before the signal level and the same reset level is referenced throughout the measurement. The 4T pixel design 10 significantly improves the performance of other CMOS image sensors, reducing both read noise and image lag. In addition, the design reduces pixel source follow offsets and the like.
However, one disadvantage with such 4T pixel designs using digital double sampling to suppress noise is that the output signals on the column circuit are doubled, effectively doubling bandwidth usage. Thus, a system and method for a CMOS image sensor is needed that reduces required output bandwidth while also suppressing kTC noise and suppressing full analog disturbances.